Bridgeless power factor correction circuit

ABSTRACT

A bridgeless power factor correction circuit as disclosed can include first and second input inductors, a series connection of a first diode and a first controllable semiconductor switch, and a series connection of a second diode and a second controllable semiconductor switch, the series connections being connected in parallel between positive and negative output terminals of the power factor correction circuit. The power factor correction circuit can include a switching circuit adapted to connect a capacitor between the input terminal and the output terminal such that the capacitor is connected between the first input terminal and a potential of the output terminal when input voltage connectable to the input terminals is positive and the capacitor is connected between the second input terminal and a potential of the output terminal when the input voltage connectable to the input terminals is negative.

RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to European PatentApplication No. 13195824.1 filed in Europe on Dec. 5, 2013, the entirecontent of which is hereby incorporated by reference in its entirety.

FIELD

The present disclosure relates to a bridgeless power factor correction(PFC) circuit, such as a PFC circuit for transforming a single-phasealternating current (AC) voltage to a direct current (DC) voltage.

BACKGROUND INFORMATION

A power factor corrector or a power factor correction circuit (PFC) is afront-end power stage of a grid-connected power converter, such as apower supply, motor drive and electronic ballast [1] to [3]. It is usedto meet international grid current standards, such as IEEE519 andIEC-61000-3-12. These standards are also applied to a single-phase gridnetwork which can be used as an AC power source for low power industrialapplications and household devices. Using a PFC in a system ensures asinusoidal input current and a stable output DC voltage. It can also beforeseen that the PFC will be a very important device to ensure a goodpower quality in a more complex grid network.

In a known PFC, a diode bridge and a boost converter are used. The diodebridge rectifies the grid current and voltage. The boost convertershapes inductor current into rectified sinusoidal current. As a result,grid current is sinusoidal and in-phase of grid voltage. This converteris simple and low-cost, since only one active switch is in the circuit.Thus, it is popularly adopted by lighting applications. However, thedrawback of the circuit is a high conduction loss for high powerapplications since there are three semiconductors in the current path,irrespective of whether the controlled switch is on or off. Moreover, alarge high frequency filter is used due to a large peak-to-peak highfrequency ripple current carrying on the gird current.

In order to solve the conduction loss issue of the known PFC, abridgeless PFC is proposed in [4]. The PFC integrates a diode bridge anda boost converter into one power stage, including two switching arms.One switching arm shapes half line cycle grid current. Two gridinductors are always in series, irrespective of the switching state. Thecircuit gives a low conductional loss, since it has only twosemiconductors in the current paths. However, it is more expensivebecause of the more active device and magnetic components. In addition,there is a grounding problem, or a common mode voltage or leakagecurrent issue, when it is operating. In addition, a high frequencyfilter is still included.

Some modifications of bridgeless PFC circuits have been proposed totackle the issue of leakage current. A bridgeless PFC with a seriessemiconductor switch is presented in [5]. The series switch issynchronized with a main switching for current shaping. Thus, gridterminals are electrically isolated during inductor current chargingstates. Then, a low leakage current can be generated. However, itinvolves one higher-rated voltage, higher-rated current and higherswitching frequency semiconductor switch in the main current flowingpath. As a result, the conduction loss is higher than the simplebridgeless PFC during inductor current discharging states. Thefundamental idea of the bridgeless PFC is distorted and it is expensive.In addition, a high frequency filter is still included.

Another method of eliminating the common mode voltage issue is to use abi-directional switch to charge up an input inductor current [6]. Whenthe bi-directional switch is closed, all diodes are off due to a reversebias by the output dc voltage. This leads to electrical isolation duringthat switching stage.

There are thus always two semiconductors in the current paths. However,as the diode bridge is switching at a high frequency, four expensivefast diodes are used. The conduction performance of a fast diode isoften not as good as that of line frequency diodes. A floating gatedrive is another cost issue for this topology. In addition, a highfrequency filter is still included.

A diode clamped bridgeless PFC is proposed in [7]. It provides a simpleand efficient solution for tackling the common mode voltage issue. Inthis bridgeless PFC, two diodes connect the circuit ground to a positiveterminal and a negative terminal of the AC power source, respectively.These two line frequency diodes guarantee that no common mode voltagedifference occurs between the ground and the AC source. However, gridinductors work in half line cycle only, which means that two separateand identical inductors are used. The high cost and large size of theinductors are problematic. In addition, a high frequency filter is stillincluded.

To address the use of expensive magnetic devices, a single core inductoris introduced in [8]. By this method, the size issue can be solved dueto the use of one magnetic core. However, the design of the inductor isvery difficult. In addition, a high frequency filter is still included.

Instead of diodes, capacitors can be used to maintain the voltagedifference between the ground and the AC power sources. A capacitorclamped bridgeless PFC is disclosed in [9]. The capacitors are coupledto the grid terminals and the ground, whereby a low leakage current canbe ensured, but a high frequency current ripple can still be found atthe grid current; thus, a high frequency filter is still included.

A built-in common filter is disclosed in [10]. In this modification, acommon mode filter connects serially with boost chokes, two capacitorsperform functions of voltage clamping and filtering. The topologyeffectively reduces leakage current, but it does not help in filteringout the high frequency components from the grid current.

An improved capacitor clamped approach is proposed in [11]. In thisdesign, two switches are used to connect the voltage clamped capacitors.According to the disclosure, the additional switches are switching atthe same time and the switches are used to improve the efficiency duringlight load operation. Thus, it can be estimated that the performanceshould be more or less the same as that of a simple capacitor clampedbridgeless PFC.

The known solutions can effectively solve the common mode voltage issueof the bridgeless PFC, but the penalties include a higher conductionloss and more or larger passive devices. Moreover, not all solutions canimprove the grid current quality.

SUMMARY

A bridgeless power factor correction circuit is disclosed, comprising:first and second input inductors (L), first ends of the inductorsforming first and second input terminals of the circuit; a seriesconnection of a first diode (D) and a first controllable semiconductorswitch (S); a series connection of a second diode (D) and a secondcontrollable semiconductor switch (S), the series connections beingconnected in parallel between positive and negative output terminals(VDC+, VDC−) of the power factor correction circuit; wherein: a secondend of the first inductor (L) is connected at a point between the seriesconnection of the first diode and the first controllable semiconductorswitch; and a second end of the second inductor (L) is connected at apoint between the series connection of the second diode and the secondcontrollable semiconductor switch; wherein polarities of the first andsecond diodes (D) are such that current can pass through the diodes tothe positive output terminal; and the controllable semiconductorswitches (S) are arranged to block current from flowing through thecontrollable semiconductor switches to the negative output terminal, thepower factor correction circuit comprising: a switching circuitconfigured to connect a capacitor (CAB; CA, CB) between the inputterminals and the output terminals of the power factor correctioncircuit in such a manner that the capacitor is connected between thefirst input terminal and a potential of the output terminals when inputvoltage connectable to the input terminals is positive, and thecapacitor is connected between the second input terminal and a potentialof the output terminals when the input voltage connectable to the inputterminals is negative.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following, disclosed features and advantages will be described ingreater detail by way of exemplary preferred embodiments, and withreference to the attached drawings, in which

FIG. 1 shows an exemplary embodiment of the present disclosure;

FIG. 2 shows exemplary implementations of bi-directional switches;

FIGS. 3 (a) and 3 (b) show switching states of an exemplary embodimentof the present disclosure during positive input voltage;

FIGS. 4 (a) and 4 (b) show exemplary equivalent circuits of FIGS. 3 (a)and 3 (b);

FIGS. 5 (a) and 5 (b) show switching states of an exemplary embodimentof the present disclosure during negative input voltage;

FIGS. 6 (a) and 6 (b) show exemplary equivalent circuits of FIGS. 5 (a)and 5 (b);

FIGS. 7, 8, 9, and 10 show exemplary embodiments of the disclosure;

FIG. 11 shows exemplary simulated waveforms of the present disclosure;

FIGS. 12 (a), (b), (c), (d), (e) show simulated waveforms of knowndevices as compared to the present disclosure; and

FIGS. 13 and 14 show basic block diagrams depicting examples involvingexemplary embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure sets forth exemplary embodiments of circuitswhich can address the issues already raised.

Exemplary embodiments are based on the idea of using one or morecapacitors and low frequency semiconductor switches in a bridgeless PFCcircuit to formulate two different LCL filter structures for differentconditions. For example, the semiconductor switches connect one or morecapacitors to the circuit in an alternating manner, depending on thepolarity of the input AC voltage.

This can reduce a grid differential mode current ripple or inductance.Further, the PFC common mode voltage can be significantly reduced, sincethe capacitor in the LCL filter clamps the voltage between the grid andthe ground.

Exemplary circuits disclosed herein need not include large inductorssince a third order filter is formed by using a switching circuit at theinput of the circuit. The high frequency components are filtered out bythe LCL filter and the filter structure is changed, depending on thepolarity of grid voltage. Because the LCL filter attenuates highfrequency components effectively, no separate EMI filter may berequired.

Exemplary circuits disclosed therein can provide a low leakage currentsince the common mode voltage is clamped by the capacitors. Further,conduction losses are low because no active or passive elements areadded to the main current path. Further, the input inductance beingsmaller, the number of turns in the inductors is also smaller. The useof low inductance inductors increases the efficiency.

FIG. 1 shows an exemplary embodiment disclosed therein. The exemplaryPFC can include a known bridgeless PFC 1 and an additional switchingcircuit 2. The switching circuit can formulate two different LCLstructures, depending on grid voltage polarity.

The bridgeless PFC 1 can include first and second input inductors L1,L2, first ends of the inductors forming first and second input terminalsof the circuit. Further, the bridgeless PFC 1 can include a seriesconnection of a first diode D1 and a first controllable semiconductorswitch S1, and a series connection of a second diode D2 and a secondcontrollable semiconductor switch S2. The series connections areconnected in parallel between positive and negative output terminalsVDC+, VDC− of the power factor correction circuit. The output terminalsform the output voltage of the circuit and, for example, a capacitor ora series connection of capacitors C1, C2 is connected between the outputterminals. As a series connection of capacitors is connected between theoutput terminals, a middle voltage potential VM is also available.

In the circuit of the exemplary embodiment, the second end of a firstinductor L1 is connected at a point between the series connection of thefirst diode and the first controllable semiconductor switch, andsimilarly the second end of a second inductor L2 is connected at a pointbetween the series connection of the second diode and the secondcontrollable semiconductor switch.

Polarities of the first and second diode D1, D2 are such that currentcan pass through the diode to the positive output terminal. That is,cathodes of the diodes are connected to the positive output terminalVDC+. The controllable semiconductor switches S1, S2 are connected suchthat the switches can block current from flowing through the switches tothe negative output terminal.

The bridgeless PFC circuit boosts the AC grid voltage to a higher DC busvoltage and controls the flow of DC power onto the DC bus. The gridcurrent is controlled sinusoidally and in-phase to the AC grid voltage.

A switching circuit 2 filters out switching frequency components whichare generated by the bridgeless PFC. The switching circuit can beadapted (i.e., configured) to connect a capacitor CAB; CA, CB between aninput terminal and an output terminal of the power factor correctioncircuit in such a manner that the capacitor is connected between thefirst input terminal and a potential of an output terminal when an inputvoltage connectable to the input terminals is positive. The capacitor isconnected between the second input terminal and a potential of an outputterminal when the input voltage connectable to the input terminals isnegative.

Specifically, in the exemplary embodiment of FIG. 1, the switchingcircuit can include two bi-directional switches SA, SB. Thebi-directional switches are, for example, connected in series and oneend of the series connection is connected to the first input terminaland the other end is connected to the second input terminal. In FIG. 1,the bridgeless PFC is shown to be connected to the input voltage VAC,whereby the first terminal is connected to Line L and the secondterminal is connected to the neutral of the grid.

The switching circuit shown in FIG. 1 can also include a capacitor CABthat is coupled between the junction point of two bi-directionalswitches SA, SB and any potential of the output terminals, (i.e., anypoint of the output DC bus). In FIG. 1, one terminal of the capacitor Vxis shown coupled to the negative output terminal, (i.e., the potentialof a negative DC bus. The capacitor is used to clamp the potentialdifference between the AC power source and the ground. The connection isshown in dashed line to highlight that the connection can also be to anyother point of the DC bus, including a positive DC bus) (i.e., thepositive output terminal, or the middle point of the output voltage VM.)

According to an exemplary embodiment, during a positive half wave of theinput voltage, the switch SA is conducting and the switch SB isblocking. During a negative half wave the switch SB is conducting andthe switch SA is blocking. Thus, during the positive half wave of theinput voltage, the capacitor is connected to the input having thepositive voltage. Similarly, during the negative half wave of the inputvoltage, the capacitor is connected to the input having the negativevoltage.

The bi-directional switches SA, SB can be realized by asingle-directional blocking semiconductor switch or by connecting twoMOSFETs back-to-back in series or other circuits and devices which canprovide bi-directional blocking and conducting characteristics. Inpractice, a body diode of a MOSFET or an anti-parallel diode of an IGBTmay create a leakage path when the semiconductor switches are turnedoff. FIG. 2 shows possible arrangements for the bi-directional switchSA, SB. Specifically, FIG. 2 (a) shows an ideal switch, (b) shows aMOSFET, (c) shows an IGBT with an anti-parallel diode, (d) shows a diodebridge with a controllable switch, (e) shows a common emitterback-to-back implementation, (f) shows a common drain back-to-backimplementation, and (g) shows a bi-directional switch formed ofanti-parallel reverse blocking IGBTs.

FIG. 3 shows exemplary switching states of the circuit of FIG. 1 duringa positive half line cycle. In this half line cycle, the filtercapacitor CAB is connected to Line L of the grid voltage through thebi-directional switch SA. The main switch S2 is always conducting andthe main switch S1 is switching at a high frequency. When the switch S1is conducting, the inductor L1 is charged, and when S1 is blocking, theinductor is boosting the output voltage.

FIGS. 3( a) and 3(b) show the circuit when the main switch S1 isswitching on and off, respectively. FIGS. 4( a) and 4(b) showcorresponding equivalent circuits of FIGS. 3( a) and 3(b), respectively.It can be seen that L1, CAB, and L2 form an LCL filter between the gridand the boost converter. In such a case, L2 takes the role of a gridinductor, and thereby a low grid deferential current ripple is achieved.Further, the capacitor CAB is coupled between Line L and the negativeterminal of the DC bus, and thereby the potential difference betweenthem is clamped, and thus a low leakage current is achieved.

During the negative half line cycle of the input voltage, again twodifferent switching states exist. In this half line cycle, the filtercapacitor CAB is connected to Neutral N of the grid voltage through thebi-directional switch SB, the main switch S1 is always conducting andthe main switch S2 is switching at a high frequency. FIGS. 5( a) and5(b) show the circuit when the main switch S2 is switching on and off,respectively. FIGS. 6( a) and 6(b) are corresponding equivalent circuitsof FIGS. 5( a) and 5(b), respectively. It can be seen that L2, CAB, andL1 form an LCL filter between the grid and the boost converter. In sucha case, L1 takes the role of a grid inductor, and a low grid deferentialcurrent ripple is achieved. Further, the capacitor CAB is coupledbetween Neutral N and the negative terminal of the DC bus and thepotential difference between them is clamped; therefore, a low leakagecurrent is achieved.

FIG. 7 shows an exemplary embodiment. In this embodiment, separateswitches SA, SB connect separate capacitors CA, CB to perform thefunctionality described above. Specifically, the switching circuitcomprises two series connections of a switch and a capacitor. A firstseries connection SA, CA is connected between the first input terminaland a potential of an output terminal. Similarly, a second seriesconnection SB, CB is connected between the second input terminal and apotential of an output terminal. In the example of FIG. 7, the otherends of the series connections are shown to be connected to negativeoutput terminal. In the embodiment, SA switches are on in the period ofthe positive half line cycle, and SB switches are on in the period ofthe negative half line cycle. The purpose of the switches is toreconfigure the LCL filter, depending on the polarity of the inputvoltage. An advantage of the topology of FIG. 7 is that allsemiconductor switches SA, SB, S1, and S2 are referenced to the ground,making it an attractive choice with respect to the design of gatedrivers.

Another exemplary embodiment is shown in FIG. 8. The switching circuitin FIG. 8 is coupled in X shape between the arms consisting of a seriesconnection of a diode and a controllable switch and the AC source. Twobi-directional switches and two capacitors are used in the circuit. Morespecifically, the first series connection of a switch SA and a capacitorCA is connected in series between the first end of the first inductorand the second end of the second inductor. The second series connectionof a switch SB and a capacitor CB is connected between the second end ofthe first inductor and the first end of the second inductor.

In the embodiment of FIG. 9, the additional switching circuit is coupledin H shape between the arms and the AC source. Only one capacitor isused in the circuit. The switching circuit of the embodiment comprisestwo series connections of controllable switches. The first of the seriesconnections SA1, SB2 is connected between the first terminals of theinductors L1, L2, and the second of the series connections SB1, SA2 isconnected between the second ends of the inductors. The capacitor CAB isconnected between the middle points of the series connections. In theembodiment of FIG. 9, the capacitor CAB is connected to the circuit byusing the switches SA1 and SA2 during a positive half cycle and theswitches SB1 and SB2 during a negative half cycle.

In the embodiments of FIGS. 8 and 9, the capacitor is connected betweenthe input terminal of the circuit and the potential of the outputterminal through the main switches of the circuit. For example, in FIG.8 during the positive half wave of the input voltage, the switch SA isconducting and the capacitor CA is connected between the first inputterminal and the negative output terminal through the switch S2 which isconducting during the positive half wave. During the negative half wave,the capacitor CB is connected to the negative output terminal throughthe switch S1.

FIG. 10 shows another exemplary embodiment, in which the switchingcircuit is formed of four switches and one capacitor. The switches arearranged such that two series connections are formed and both of theseries connections are connected over the inductances L1, L2 of theinput. The capacitor CAB is connected between the middle points of theseries connections of the switches. As in the embodiment of FIG. 9, theswitches SA1, SA2 are controlled conductive during the positive halfcycle of the input voltage, thereby connecting the capacitor between thefirst end of the first inductor and the second end of the secondinductor. During the positive half cycle, the second end of the secondinductor is connected to the potential of the negative output terminalthrough the conducting switch S2. During the negative half cycle, theswitches SB1 and SB2 are controlled conductive, thereby connecting thecapacitor CAB between the first end of the second inductor and thesecond end of the first inductor.

In the following, the performance of an exemplary bridgeless PFCdisclosed herein is demonstrated by computer simulations. The simulatedsystem corresponds to that of FIG. 1. The input source can include(e.g., consist of) a single-phase AC voltage source, and the output is aresistor. The simulated output power of the PFC is 2.2 kW, the output DCvoltage is 380 V, the line frequency is 50 Hz, and the input AC voltageis 230 Vrms. The switching frequency is 20 kHz. All semiconductors andinductors are ideal components.

FIG. 11 shows exemplary key simulated waveforms. It can be seen that thegrid current (Iin, second plot) is shaped sinusoidal and in-phase to thegrid voltage (first plot). Also, the current ripple is very small. Theleakage current (I(Ccm), fourth plot) is small as well. The third plotshows the output voltage.

FIG. 12 shows a comparison of exemplary current waveforms usingdifferent clamping techniques in a bridgeless PFC. In the figures, thefirst row of waveforms is a grid current, the second row of waveforms isan inductor current, and the bottom row of waveforms is a leakagecurrent. The inductance and switching frequency are the same in thiscomparison.

FIG. 12( a) shows waveforms of a known bridgeless PFC which is presentedin [4]. The grid current (Iin) carries a large high frequency currentripple, and the leakage current is high as well (approximately 5 A).

FIG. 12( b) shows diode clamped bridgeless PFC currents, thecorresponding topology being presented in [7]. The leakage current isminimized, almost to OA, but the grid current ripple is higher than inthe conventional one, since only one inductor is in the current path.

FIG. 12( c) shows capacitor clamped bridgeless PFC currents, thecorresponding topology being presented in [9]. The leakage current isminimized to an acceptable range, 0.2 A_peak, but the grid currentripple is still as high as in the known one.

FIG. 12( d) shows an exemplary capacitor clamped plus a common modefilter bridgeless PFC currents, the corresponding topology beingpresented in [10]. The leakage current is further minimized, to 0.02A_peak, but to no avail as far as the grid current ripple is concerned.

FIG. 12( e) shows exemplary waveforms of the bridgeless PFC of thepresent invention, the corresponding topology being presented in FIG. 1.The leakage current is slightly higher than in the prior art solutionsbut still in an acceptable range, (approximately 0.4 A_peak); moreover,a high quality grid current is obtained. It can be seen that the PFC ofthe present disclosure can be superior to the known solutions in termsof high quality grid current and low leakage current.

Exemplary embodiments can be usable in connection with an apparatus forsourcing AC power from an AC power grid to a DC load, such as a motordrive. FIG. 13 and FIG. 14 depict conceptual block diagrams of anexemplary two-stage power converter used to convert AC power from asingle-phase grid into DC power suitable for driving an electrical load.The first stage of a power converter can include a Power FactorCorrector (PFC), such as a bridgeless PFC, that outputs DC power onto aDC bus. The second stage of the power converter can be an inverter (FIG.14) or a DC-to-DC converter (FIG. 13) that supplies the power to a load.The voltage levels indicated in FIGS. 13 and 14 are examples of acommonly employed voltage.

It will be apparent to those skilled in the art that as technologyadvances, the inventive concepts disclosed herein can be implemented invarious ways. The invention and its embodiments are not limited to theexamples described herein but may vary within the scope of the claims.

Thus, it will be obvious to a person skilled in the art that theinventive concept can be implemented in various ways. The invention andits embodiments are not limited to the examples described above but mayvary within the scope of the claims.

It will be appreciated by those skilled in the art that the presentinvention can be embodied in other specific forms without departing fromthe spirit or essential characteristics thereof. The presently disclosedembodiments are therefore considered in all respects to be illustrativeand not restricted. The scope of the invention is indicated by theappended claims rather than the foregoing description and all changesthat come within the meaning and range and equivalence thereof areintended to be embraced therein.

REFERENCES

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1. A bridgeless power factor correction circuit, comprising: first andsecond input inductors (L), first ends of the inductors forming firstand second input terminals of the circuit; a series connection of afirst diode (D) and a first controllable semiconductor switch (S); aseries connection of a second diode (D) and a second controllablesemiconductor switch (S), the series connections being connected inparallel between positive and negative output terminals (VDC+, VDC−) ofthe power factor correction circuit; wherein: a second end of the firstinductor (L) is connected at a point between the series connection ofthe first diode and the first controllable semiconductor switch; and asecond end of the second inductor (L) is connected at a point betweenthe series connection of the second diode and the second controllablesemiconductor switch; wherein polarities of the first and second diodes(D) are such that current can pass through the diodes to the positiveoutput terminal; and the controllable semiconductor switches (S) arearranged to block current from flowing through the controllablesemiconductor switches to the negative output terminal, the power factorcorrection circuit comprising: a switching circuit configured to connecta capacitor (CAB; CA, CB) between the input terminals and the outputterminals of the power factor correction circuit in such a manner thatthe capacitor is connected between the first input terminal and apotential of the output terminals when input voltage connectable to theinput terminals is positive, and the capacitor is connected between thesecond Input terminal and a potential of the output terminals when theinput voltage connectable to the input terminals is negative.
 2. Abridgeless power factor correction circuit as claimed in claim 1,wherein the switching circuit is arranged to form a conduction path forhigh-frequency current components from an input of the circuit through acapacitor to the potential of the output terminals.
 3. A bridgelesspower factor correction circuit as claimed in claim 1, wherein theswitching circuit comprises: two controllable bidirectional switches(SA, SB) and a capacitor (CAB), the switches being connected in seriesbetween the first and second input terminals and the capacitor beingconnected between a connection point between the controllable switchesand a potential of the output terminals.
 4. A bridgeless power factorcorrection circuit as claimed in claim 1, wherein the switching circuitcomprises: first and second controllable switches (SA, SB) and first andsecond capacitors (CA, CB), the first controllable switch and the firstcapacitor being connected in series between the first input terminal anda potential of the output terminals, and the second controllable switchand the second capacitor being connected in series between the secondinput terminal and a potential of the output terminals.
 5. A bridgelesspower factor correction circuit as claimed in claim 1, wherein theswitching circuit comprises: first and second controllable switches (SA,SB) and first and second capacitors (CA, CB), the first controllableswitch and the first capacitor being connected in series between thefirst input terminal and the second end of the second inductor (L), andthe second controllable switch and the second capacitor being connectedin series between the second input terminal and the second end of thefirst inductor (L).
 6. A bridgeless power factor correction circuit asclaimed in claim 1, wherein the switching circuit comprises: first andsecond controllable switch pairs (SA, SB), and a capacitor (CAB), thecontrollable switches of the switch pairs being connected such that afirst switch (SA) of the first switch pair is connected in series with asecond switch (SB) of the second switch pair and this series connectionis connected between the first and second input terminals, and a firstswitch (SB) of the second switch pair is connected in series with asecond switch (SA) of the first switch pair and this series connectionis connected between the second ends of the first and second inductors,and the capacitor (CAB) is connected between connection points of theseries connection of the controllable switches, wherein the first switchpair (SA) is arranged to be controlled conductive when the input voltageconnectable to the input terminals is positive and the second switchpair (SB) is arranged to be controlled conductive when the input voltageconnectable to the input terminals is negative.
 7. A bridgeless powerfactor correction circuit as claimed in claim 1, wherein the switchingcircuit comprises: first and second controllable switch pairs (SA, SB)and a capacitor (CAB), the controllable switches of the switch pairsbeing connected such that a first switch (SA) of the first switch pairis connected in series with a first switch (SB) of the second switchpair and this series connection is connected between the first andsecond ends of the first inductor (L), and a second switch (SA) of thesecond switch pair is connected in series with a second switch (SB) ofthe second switch pair and this series connection is connected betweenthe first and second ends of the second inductor (L), and the capacitor(CAB) is connected between the connection points of the seriesconnection of the controllable switches, wherein the first switch pair(SA) is adapted to be controlled conductive when the input voltageconnectable to the input terminals is positive and the second switchpair (SB) is adapted to be controlled conductive when the input voltageconnectable to the input terminals is negative.
 8. A bridgeless powerfactor correction circuit as claimed in claim 1, wherein a potential ofthe output terminals is the potential of a second output terminal, afirst output terminal or a potential between voltages of the firstoutput terminal and the second output terminal.
 9. A bridgeless powerfactor correction circuit as claimed in claim 1, wherein the capacitoris connected between the input terminal and a potential of the outputterminals through the first or second controllable semiconductor switch(S1, S2).
 10. A bridgeless power factor correction circuit as claimed inclaim 2, wherein the switching circuit comprises: two controllablebidirectional switches (SA, SB) and a capacitor (CAB), the switchesbeing connected in series between the first and second input terminalsand the capacitor being connected between a connection point between thecontrollable switches and a potential of the output terminals.
 11. Abridgeless power factor correction circuit as claimed in claim 2,wherein the switching circuit comprises: first and second controllableswitches (SA, SB) and first and second capacitors (CA, CB), the firstcontrollable switch and the first capacitor being connected in seriesbetween the first input terminal and a potential of the outputterminals, and the second controllable switch and the second capacitorbeing connected in series between the second input terminal and apotential of the output terminals.
 12. A bridgeless power factorcorrection circuit as claimed in claim 2, wherein the switching circuitcomprises: first and second controllable switches (SA, SB) and first andsecond capacitors (CA, CB), the first controllable switch and the firstcapacitor being connected in series between the first input terminal andthe second end of the second inductor (L), and the second controllableswitch and the second capacitor being connected in series between thesecond input terminal and the second end of the first inductor (L). 13.A bridgeless power factor correction circuit as claimed in claim 2,wherein the switching circuit comprises: first and second controllableswitch pairs (SA, SB) and a capacitor (CAB), the controllable switchesof the switch pairs being connected such that a first switch (SA) of thefirst switch pair is connected in series with a second switch (SB) ofthe second switch pair and this series connection is connected betweenthe first and second input terminals, and a first switch (SB) of thesecond switch pair is connected in series with a second switch (SA) ofthe first switch pair and this series connection is connected betweenthe second ends of the first and second inductors, and the capacitor(CAB) is connected between connection points of the series connection ofthe controllable switches, wherein the first switch pair (SA) isarranged to be controlled conductive when the input voltage connectableto the input terminals is positive and the second switch pair (SB), isarranged to be controlled conductive when the input voltage connectableto the input terminals is negative.
 14. A bridgeless power factorcorrection circuit as claimed in claim 2, wherein the switching circuitcomprises: first and second controllable switch pairs (SA, SB) and acapacitor (CAB), the controllable switches of the switch pairs beingconnected such that a first switch (SA) of the first switch pair isconnected in series with a first switch (SB) of the second switch pairand this series connection is connected between the first and secondends of the first inductor (L), and a second switch (SA) of the secondswitch pair is connected in series with a second switch (SB) of thesecond switch pair and this series connection is connected between thefirst and second ends of the second inductor (L), and the capacitor(CAB) is connected between the connection points of the seriesconnection of the controllable switches, wherein the first switch pair(SA) is adapted to be controlled conductive when the input voltageconnectable to the input terminals is positive and the second switchpair (SB) is adapted to be controlled conductive when the input voltageconnectable to the input terminals is negative.
 15. A bridgeless powerfactor correction circuit as claimed in claim 2, wherein a potential ofthe output terminals is the potential of a second output terminal, afirst output terminal or a potential between voltages of the firstoutput terminal and the second output terminal.
 16. A bridgeless powerfactor correction circuit as claimed in claim 3, wherein a potential ofthe output terminals is the potential of a second output terminal, afirst output terminal or a potential between voltages of the firstoutput terminal and the second output terminal.
 17. A bridgeless powerfactor correction circuit as claimed in claim 4, wherein a potential ofthe output terminals is the potential of a second output terminal, afirst output terminal or a potential between voltages of the firstoutput terminal and the second output terminal.
 18. A bridgeless powerfactor correction circuit as claimed in claim 2, wherein the capacitoris connected between the input terminal and a potential of the outputterminals through the first or second controllable semiconductor switch(S1, S2).
 19. A bridgeless power factor correction circuit as claimed inclaim 2, wherein the capacitor is connected between the input terminaland a potential of the output terminals through the first or secondcontrollable semiconductor switch (S1, S2).
 20. A bridgeless powerfactor correction circuit as claimed in claim 2, wherein the capacitoris connected between the input terminal and a potential of the outputterminals through the first or second controllable semiconductor switch(S1, S2).